Logic Design - How to write simple RAM in VHDL by drifter1

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vhdl · @drifter1 · (edited)
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Logic Design - How to write simple RAM in VHDL
<html>
<p><img src="https://s22.postimg.cc/kin7t5ltd/Thumbnail.png" width="800" height="800"/></p>
<p>Custom thumbnail using:</p>
<ul>
  <li><a href="https://www.iconfinder.com/icons/202807/blocks_ram_icon#size=512">RAM</a></li>
  <li><a href="https://www.istockphoto.com/photos/circuit-board?excludenudity=true&amp;mediatype=photography&amp;phrase=circuit%20board&amp;sort=mostpopular">Circuit</a></li>
</ul>
<h2>Introduction</h2>
<p>Hello Steemians it's a me Drifter Programming!<br>
&nbsp;&nbsp;&nbsp;Today we get back to <strong>Logic Design</strong> to talk about the <strong>implementation of many simply types of RAM</strong> in the Hardware Description Language (HDL) that we covered during my series which is <strong>VHDL</strong>! (I promised to do Verilog also and it will come in the following Weeks I promise!)</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;To understand what I will be talking about I highly suggest you to refresh your knowledge using my series that contains simulating the circuits and even the implementation of more complex units like the ALU that does mathematical operations for CPU's!</p>
<p>You &nbsp;can find the previous posts in my <a href="https://steemit.com/recap/@drifter1/recap-spring-2018">recap</a>!</p>
<p>So, without further do, let's get RAMing! xD</p>
<p><br></p>
<h2>RAM architecture and types</h2>
<p>So, let's start with the simple question:<br>
<strong>What is RAM?</strong></p>
<p><br></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;RAM is defined as <strong>Random-Access Memory</strong> and <strong>allows us to read and write</strong> <strong>information </strong>to a physical location inside of the RAM which is the so called <strong>memory array</strong>.</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Lots and lots of types of RAM are out there nowadays, but an <strong>basic separation</strong> can be done by saying that there are:</p>
<ul>
  <li><strong>Static </strong>RAM's (SRAM)</li>
  <li><strong>Dynamic </strong>RAM's (DRAM)</li>
</ul>
<h3>Static RAM</h3>
<p>&nbsp;&nbsp;&nbsp;&nbsp;SRAM is static, which means that it has a specific number of memory cells that build up the memory array. This of course means that it's more expensive to produce (more transistors, cause each bit of data is stored in a specific predefined location), but also faster and less power consuming than DRAM.</p>
<p>This type of RAM is mostly used in Cache memory of CPU's.</p>
<h3>Dynamic RAM</h3>
<p>&nbsp;&nbsp;&nbsp;&nbsp;DRAM is stores the bits (information) using a transistor-capacitor pair which create a so called DRAM cell. This means that the capacitor will either be charged (1) or not charged (0) and that the access is defined using&nbsp;the transistor that acts like a switch that let's us "read/write" the capacitor or not.</p>
<p>Because it's less expensive to build it's the predominant form of computer memory nowadays!</p>
<p>Some information from <a href="https://en.wikipedia.org/wiki/Random-access_memory#Types_of_random-access_memory">wikipedia</a>.</p>
<p><br></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Either way any <strong>RAM is considered volatile</strong>, cause it loses it's state and so information whenever there is a power loss or reset. To store information permanently we use another type of memory called ROM, that I will cover next time!</p>
<p><br></p>
<h3>RAM I/O</h3>
<p>We covered the basic types of RAM, but what is the I/O of RAM?</p>
<p>Of course <strong>RAM communicates using the following</strong>:</p>
<ul>
  <li>Data Input -&gt; information to write</li>
  <li>Data Output -&gt; information to read</li>
  <li>Address -&gt; we need to know where to read or write</li>
  <li>Read/Write -&gt; specifying if we want to read or write from an address</li>
  <li>Enable -&gt; we enable the RAM only when needed to "save power".</li>
  <li>Clock -&gt; RAM is of course a synchronous circuit and so needs a Clock Input&nbsp;</li>
</ul>
<p><br></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Depending on the application we may want to read and write at the same time, and maybe even on different addresses. This can of course be done by having 2 addresses and two separate read and write signals.</p>
<p>This means that RAM can also be splitted into these <strong>categories</strong>:</p>
<ul>
  <li>Single-Port RAM with separate read and write signals (no enable needed)&nbsp;</li>
  <li>Single-Port RAM with a single read/write signal and RAM enable</li>
  <li>Dual-Port RAM with separate signals (that may be combined R/W signals) for each "line"</li>
</ul>
<p>&nbsp;&nbsp;&nbsp;&nbsp;We can of course continue on&nbsp;and insert 3, 4 or even more lines as we wish, but I guess that after a point a second or even third memory might be better.</p>
<p><br></p>
<h3>Combined R/W or not</h3>
<p>&nbsp;&nbsp;&nbsp;&nbsp;You can see that the read/write signal can be defined as a combined signal or as two separate ones, but when do we use each one?</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;RAM is a synchronous circuit which means that the information will be stored into it (or the requested send to the output) after a clock event...</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;If the application we have needs to be able to <strong>read at the same clock</strong> without having to wait for a clock event or even a whole clock period, then we can <strong>simply define only a write signal </strong>(1 -&gt; write, 0 -&gt; not write) and make the <strong>output show us directly what the specified address has</strong>, which means that we <strong>read all the times</strong>, without having to specify that we want to! Keep in mind that this implementation should contain a memory enable signal!</p>
<p><br></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;In VHDL we will of course only implement static RAM that is build up of memory cells and so creates a memory array.</p>
<p>So, let's get into the implementation of these 3 categories we talked about.</p>
<h2>VHDL implementation of Single-Port RAM with Read and Write signals</h2>
<p>The <strong>VHDL code </strong>looks like this:</p>
<p><img src="https://s22.postimg.cc/h5t7uwva9/code_1.jpg" width="1109" height="800"/></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;You can see that I used the generic declaration to specify the address length and data length, so that it's easier to edit those values afterwards.</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Also, note that I use a conv_integer() function that takes in the address which is in binary and converts it to an integer which is used in the declaration of the memory array!</p>
<p>The actual memory array is a user-defined type of 2^n- bit memory celss for a n-bit address.</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;You can see that when reading or writing we have to set the specific "enable" signal to '1', cause else nothing is gonna happen.</p>
<p><br></p>
<p>Here a small <strong>simulation using Modelsim</strong>:</p>
<p><img src="https://s22.postimg.cc/hikm148f5/run_1.jpg" width="1280" height="664"/></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;You can see that I first define the clock signal using the "right-click"-technique and that I then write and read the value "10100110" into/from the address "00000000".</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Note that stuff gets written or read only on a rising edge of a clock and so the yellow-line is the point where we "read". Because the clock starts with '1' we of course "write" directly!</p>
<p><br></p>
<h2>VHDL Implementation of Single-Port RAM with one combined R/W signal and RAM enable</h2>
<p>&nbsp;&nbsp;&nbsp;&nbsp;To make it even more interesting let's make it so that we read with '0' and just keep the then specified address in a temporary signal and simply send this directly to the output all the times!</p>
<p>The <strong>VHDL code</strong> looks like this:</p>
<p><img src="https://s22.postimg.cc/vu446ho5t/code_2.jpg" width="1009" height="800"/></p>
<p>We simply need a combined r/w signal and a mem_enable signal.</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;To make it easier for us to output what we read we also specify a temp_address signal which will store the last address for which we have rw_enable = '0' (read) and so outputs the information of that address to data_output!</p>
<p><br></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Running it for another input and address you can see that we again have to wait for a rising edge, but this time the write/read signal is actually the same signal and specifying if we want to do something in general is of course done using the mem_enable signal.</p>
<p>Here a <strong>Modelsim simulation graph</strong>:</p>
<p><img src="https://s22.postimg.cc/fvvegd1nl/run-2.jpg" width="1280" height="260"/></p>
<p><br></p>
<h3>VHDL implementation of Dual-Port RAM with Combined Read and Write signals</h3>
<p>To do this we simply have to "duplicate" the previous design!</p>
<p>The <strong>code </strong>looks like this:</p>
<p><img src="https://s22.postimg.cc/i9hxkl2q9/code_3.jpg" width="635" height="800"/></p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;From all the stuff duplicates and to make it easy to enable/disable the ports I also included a new port_enable signal for each line!</p>
<p><br></p>
<p>Let's <strong>simulate </strong>it so that port1 writes and port2 reads from the same address:</p>
<p><img src="https://s22.postimg.cc/hjz588pc1/run_3.jpg" width="1280" height="645"/></p>
<p><br></p>
<p>You can find all the <strong>codes </strong>that I implemented here on <strong>pastebin</strong>:</p>
<ul>
  <li><a href="https://pastebin.com/pGky4ZMs">Single Port Ram with separate R/W</a></li>
  <li><a href="https://pastebin.com/pEUTSQ0q">Single Port Ram with combined R/W</a></li>
  <li><a href="https://pastebin.com/ND8Pm8ND">Dual Port Ram with combined R/W signals</a></li>
</ul>
<p><br></p>
<h2>How and when to use RAM in your designs</h2>
<p>So, that's cool and all, but when should you use it?</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Well, whenever you have ton of information<strong> it's not good if you store information directly into registers</strong>, cause registers make the design more expensive and also can't store that much and so you end up with a ton of registers!</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;This means that<strong> large information should be stored into RAM</strong> modules that should have the right data-size and also that exact "space" that you need to store your stuff.</p>
<p>Ok, so this covers when, but how do we use it?</p>
<p>Well, this is of course more complicated...</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;To manage RAM we have to create a FSM (finite-state-machine) or control unit that sends signals to the different modules of our design and organizes, synchronizes our workflow. Or we could also send the signal directly from the module that wants to store.</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;For example a multplier or adder could send a write-signal to the memory and store the calculated result into the memory. The problem would be managing the address for which an FSM (which could even be a simple binary counter) has to be used.</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;I guess that it's really up to you to how you will use it and of course the amount of lines, exact type of RAM, and maybe even unique signals can be changed, tweaked etc. by you any time when you think that it might help with the performance of your circuit!</p>
<blockquote>Always remember faster and smaller is what we need in Internet of Things (IoT) nowadays!</blockquote>
<p><br></p>
<p>And this is actually it and I hope that you enjoyed it!</p>
<p>&nbsp;&nbsp;&nbsp;&nbsp;Next time I think of covering how we implement ROM (read-only memory), cause a lot of times information just has to be read and we don't have to re-write stuff to the memory!</p>
<p>Bye!</p>
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vote details (193)
@dexterdev ·
$0.08
You reminded me my M Tech days. I used to struggle with VHDL. Its nice to see these topics in steemit. I will wait for more similar stuff. Maybe you can upload your codes in github too. :)
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@drifter1 ·
$0.07
I plan to make something more advanced in the near future!
I will keep github in mind, but I guess it will just be a small series here on steemit!
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@tts · 
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@utopian-io ·
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#### Hi @drifter1!

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@trumpman ·
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Vhdl is for noobs
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@drifter1 ·
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burn him! :P
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@shirosh ·
$0.07
Thanks for the tutorial @drifter1. Could you please do tutorial for VHDL image processing.
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vote details (1)
@drifter1 ·
$0.07
Haha is that maybe some homework that you have?

First, specify the processing, what kind of processing do we have to do to the image?

Either way I guess the **steps** needed are: 
* store the image pixels in a RAM
* do some processing using a processing unit
* write the "output" to the same or another RAM or even some output device

Are you maybe talking about Shaders for a GPU?

I guess I need a better "description" of the problem, so that I can implement what exactly you want...which means:
*What is it that you want me to implement?*
:)
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@drsensor ·
$0.07
Ah... VHDL, Xilinx, FPGA, State Machine, and red raport 😂
I hope I can see this kind of tutorial to reminiscing the old day.
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@drifter1 ·
$0.07
Oh no you got me!

I'm thinking of implementing something "big" that will of course contain a State machine (FSM) and will then be uploaded to a Xilinx FPGA (I will buy a relatively good one in the Summer).

So, be prepared! More is yet to come!
This is just the beginning :D
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root_title"Logic Design - How to write simple RAM in VHDL"
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